1. Field of the Invention
The present invention relates to a method for fabricating a CMOS, and more particularly, to a method for fabricating a CMOS using ion implantation processes.
2. Discussion of the Related Art
A scaled-down CMOS device has several drawbacks such as punch-through between the source and drain in a short channel MOSFET, latch-up in a CMOS circuit, and degradation of insulation characteristics due to the punch-through between devices. These problems need to be solved to attain a successful scaled-down semiconductor CMOS device. One proposed solution to these problems involves a method of performing a punch-through-stop-ion implantation on a semiconductor substrate before forming a gate electrode in order to improve the punch-through characteristics of a short channel MOSFET. Also, in order to solve the latch-up problem, a retrograde well doping method is performed using a high energy ion implantation. A field channel stop doping method is performed before forming a field oxide in order to improve insulation characteristics.
However, the above proposed solutions require many trade-offs in fabricating CMOS integrated circuits such as complicated fabrication including many ion implantation steps, increased fabrication costs, degradation in characteristics due to the increase in concentration of MOSFET channel regions by a punch-through doping step, reduced speed due to reduced carrier mobility and increased junction capacitance, reduced active width due to dopant encroachment from a field region to an active region by a field transistor channel stop doping step, and increased threshold voltage of the transistor. Therefore, research has been needed to reduce fabrication costs and to prevent degradation of device characteristics in scaled down semiconductor devices.
A conventional CMOS fabrication method will now be described with reference to the accompanying drawings.
Referring to FIG. A, a first insulation layer 112 made of SiO.sub.2 is formed on a substrate 111, and a second insulation layer 113 made of silicon nitride (Si.sub.3 N.sub.4) is formed on first insulation layer 112.
Referring to FIG. 1B, second insulation layer 113 (Si.sub.3 N.sub.4) of a potential n-well portion is removed, and a photoresist 114 is deposited on second insulation layer 113 (Si.sub.3 N.sub.4) at the portion excluding the potential n-well portion. P.sup.+ ions are implanted to form an n-well 116, as shown in FIG. 1C.
First insulation layer 112 (SiO.sub.2) is cultivated to form a field oxide 115, and n-well 116 is cultivated. Boron (B.sup.+) ions are implanted over the structure in order to form a p-well 117 under first insulation layer 112 (SiO.sub.2) with the potential n-well 116 remaining, as shown in FIG. 1C. P-well 117 is formed on the portion of the substrate 111 excluding the cultivated thick portion of field oxide 115.
Referring to FIG. 1D, field oxide 115 is partially removed to make the thickness thereof same as that of first insulation layer 112, thereby re-forming first insulation layer 112 on wells 116 and 117.
Referring to FIG. 1E, a second photoresist 118 is deposited above the middle portion of P-well 117 and above n-well 116. Phosphorus ions (P.sup.+) are implanted into n-well 116 to perform a field channel stop ion implantation forming N.sup.+ regions 119.
Referring to FIG. 1F, a third photoresist 121 is deposited above the whole surface of p-well 117 and middle portion of n-well 116, and boron ions (B.sup.+) are implanted to perform a field channel stop ion implantation forming p.sup.+ regions 120.
Referring to FIG. 1G, a fourth photoresist 122 is deposited above n-well 116 and boron fluoride BF.sub.2 is implanted into p-well 117 to perform a threshold voltage controlling ion implantation.
Fourth photoresist 122 deposited above n-well 116 is removed, a fifth photoresist 123 is deposited above p-well 117, and boron fluoride BF.sub.2 is implanted into n-well 116 for performing the threshold voltage controlling ion implantation, as shown in FIG. 1H. Fifth photoresist 123 is removed to complete the threshold voltage controlling ion implantation processes for n-well 116 and p-well 117, as shown in FIG. 1I.
In order to form a gate for n-well 116, an n.sup.+ polysilicon layer 124 is formed on field oxides 115 and initial oxides 112 and a gate oxide layer 125 is formed on n.sup.+ polysilicon layer 124. A sixth photoresist 126 is selectively deposited on a part of gate oxide layer 125 where the MOSFET gate will later be formed, as shown in FIG. 1J.
Gate oxide 125 and n.sup.+ polysilicon layer 124 are etched, excluding the portions underneath sixth photoresist 126. Sixth photoresist 126 is removed to complete a p-MOSFET gate above a middle portion of n-well 116, as shown in FIG. 1K.
In order to form a gate of an MOSFET, a p.sup.+ polysilicon layer 127 is deposited on field oxides 115 and initial oxides 112 and a gate oxide layer 128 is formed on p.sup.+ polysilicon layer 127. A seventh photoresist 129 is selectively deposited above a middle portion of p-well 117, as shown in FIG. 1L.
Seventh photoresist 129 is etched excluding the lower portion thereof to leave p.sup.+ polysilicon layer 130 and gate oxide layer 131, thereby completing an n-MOSFET gate, as shown in FIG. 1M.
In order to form a source 132 and a drain 133 of the p-MOS, an eighth photoresist 134 is deposited on p-well 117, as shown in FIG. 1N. Referring to FIG. 1N, boron ions (B.sup.+) are implanted over n-well 116 to form p.sup.+ source 132 and drain 133 between field oxides 115 of n-well 116 and gate 124.
Referring to FIG. 10, a ninth photoresist 137 is deposited on n-well 116. Phosphorus ions (P.sup.+) are implanted over p-well 117 to form n.sup.+ MOS source 135 and drain 136 between field oxides of p-well 117 and gate 130.
Ninth photoresist 137 is removed to finally complete the conventional CMOS, as shown in FIG. 1P.
FIG. 2 is a cross-sectional view of a conventional MOSFET for explaining the punch-through phenomenon. In FIG. 2, if a voltage is applied between source 140 and drain 141 and is gradually increased, of junctions between source 140 and drain 141 and between wells, the width of depletion regions 142 of the junction well is increased. Particularly, the depletion increase becomes maximum at the portion not having the effect of the voltage reaching from a gate to a substrate and the corner of the source/drain junction where electric fields are concentrated. If the depletion regions of source 140 and drain 141 are interconnected, carriers may rapidly move from source 140 to drain 141 through the depletion layer. Thus, if the punch-through phenomenon of an MOSFET occurs within an operating voltage, the MOSFET will become defective.
As described above, according to the conventional technique, if the concentration of wells is increased or a punch-through-stop-ion implantation is performed in order to eliminate the punch-through of the scaled-down device, the concentration of undesired MOSFET channel regions is increased, thereby reducing the speed, mobility and junction capacitance characteristics of the MOSFET. If a channel stop doping process is performed before forming a field oxide layer between active regions of an MOSFET, the space of the active regions will be reduced, thereby decreasing a current driving concentration of the MOSFET.
Moreover, the conventional method involves many complicated ion implantation processes such as a punch-through-stop-ion implantation and field channel stop implantation of an active device, a threshold voltage implantation of an MOSFET, and a retrograde implantation for improving a latch-up. Accordingly, the fabrication cost is considerably increased.